Segger J-Link - Page 33

J-Link / J-Trace (UM08001) © 2004-2017 SEGGER Microcontroller GmbH & Co. KG
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1.3.2.3 Hardware versions
Versions 1-4 (Obsolete)
Obsolete.
Version 5.0 (Obsolete)
Identical to version 4.0 with the following exception:
• Uses a 32-bit RISC CPU.
• Maximum download speed (using DCC) is over 700 Kbytes/second.
• JTAG speed: Maximum JTAG frequency is 12 MHz; possible JTAG speeds are:
48 MHz / n, where n is 4, 5, ..., resulting in speeds of:
12.000 MHz (n = 4)
9.600 MHz (n = 5)
8.000 MHz (n = 6)
6.857 MHz (n = 7)
6.000 MHz (n = 8)
5.333 MHz (n = 9)
4.800 MHz (n = 10)
• Supports adaptive clocking.
Version 5.2 (Obsolete)
Identical to version 5.0 with the following exception:
• Target interface: RESET is open drain.
Version 5.3 (Obsolete)
Identical to version 5.2 with the following exception:
• 5V target supply current limited
5V target supply (pin 19) of Kick-Start versions of J-Link is current monitored
and limited. J-Link automatically switches off 5V supply in case of over-current to
protect both J-Link and host computer. Peak current (<= 10 ms) limit is 1A,
operating current limit is 300mA.
HIGH level input voltage (V
IH
)V
IH
>= 60% of V
IF
For 1.8V <= V
IF
<= 3.6V
LOW level output voltage (V
OL
) with a
load of 10 kOhm
V
OL
<= 10% of V
IF
HIGH level output voltage (V
OH
) with a
load of 10 kOhm
V
OH
>= 90% of V
IF
For 3.6 <= V
IF
<= 5V
LOW level output voltage (V
OL
) with a
load of 10 kOhm
V
OL
<= 20% of V
IF
HIGH level output voltage (V
OH
) with a
load of 10 kOhm
V
OH
>= 80% of V
IF
JTAG/SWD Interface, Timing
SWO sampling frequency Max. 7.5 MHz
Data input rise time (T
rdi
)T
rdi
<= 20ns
Data input fall time (T
fdi
)T
fdi
<= 20ns
Data output rise time (T
rdo
)T
rdo
<= 10ns
Data output fall time (T
fdo
)T
fdo
<= 10ns
Clock rise time (T
rc
)T
rc
<= 3ns
Clock fall time (T
fc
)T
fc
<= 3ns
Table 1.1: J-Link specifications