330 CHAPTER 12 RDI
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
12.3.1.3 Debugging on Cortex-M3 devices
The RDI protocol has only been specified by ARM for ARM 7/9 cores. For Cortex-M
there is no official extension of the RDI protocol regarding the register assignement,
that has been approved by ARM. Since IAR EWARM version 5.11 it is possible to use
J-Link RDI for Cortex-M devices because SEGGER and IAR have come to an agree-
ment regarding the RDI register assignment for Cortex-M. The following table lists
the register assignment for RDI and Cortex-M:
Register
Index
Assigned register
0R0
1R1
2R2
3R3
4R4
5R5
6R6
7R7
8R8
9R9
10 R10
11 R11
12 R12
13 MSP / PSP (depending on mode)
14 R14 (LR)
16 R15 (PC)
17 XPSR
18 APSR
19 IPSR
20 EPSR
21 IAPSR
22 EAPSR
23 IEPSR
24 PRIMASK
25 FAULTMASK
26 BASEPRI
27 BASEPRI_MAX
28 CFBP (CONTROL/FAULT/BASEPRI/PRIMASK)
Table 12.1: Cortex-M register mapping for IAR + J-Link RDI
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