50 CHAPTER 1 Introduction
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
1.6.2.1 Limitations of PC-side implementations
• Instability, especially on slow targets
Due to the fact that a lot of USB transactions would cause a very bad perfor-
mance of J-Link, PC-side implementations are on the assumption that the CPU/
Debug interface is fast enough to handle the commands/requests without the
need of waiting. So, when using the PC-side-intelligence, stability cannot be
guaranteed in all cases, especially if the target interface speed (JTAG/SWD/...) is
significantly higher than the CPU speed.
• Poor performance
Since a lot more data has to be transferred over the host interface (typically
USB), the resulting download speed is typically much lower than for implementa-
tions with intelligence in the firmware, even if the number of transactions over
the host interface is limited to a minimum (fast mode).
• No support
Please understand that we cannot give any support if you are running into prob-
lems when using a PC-side implementation.
Note: Due to these limitations, we recommend to use PC-side implementations
for evaluation only.
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