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Peripheral Frame Registers
Table 5-2. Peripheral Frame 1 Registers (continued)
Name Address Range Size (x16) Access Type
(1)
GPIO Control Registers 0x6F80 - 0x6FBF 128 EALLOW-protected
GPIO Data Registers 0x6FC0 - 0x6FDF 32 Not EALLOW-protected
GPIO Interrupt and LPM Select 0x6FE0 - 0x6FFF 32 EALLOW-protected
Registers
Table 5-3. Peripheral Frame 2 Registers
Name Address Range Size (x16) Access Type
(1)
System Control Registers 0x7010 - 0x702F 32 EALLOW-protected
SPI-A Registers 0x7040 - 0x704F 16 Not EALLOW-protected
SCI-A Registers 0x7050 - 0x705F 16 Not EALLOW-protected
External Interrupt Registers 0x7070 - 0x707F 32 Not EALLOW-protected
ADC Registers 0x7100 - 0x711F 32 Not EALLOW-protected
SCI-B Registers 0x7750 - 0x775F 16 Not EALLOW-protected
SCI-C Registers 0x7770 - 0x777F 16 Not EALLOW-protected
I2C Registers 0x7900 - 0x793F 64 Not EALLOW-protected
(1)
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data can be returned or written).
Table 5-4. Peripheral Frame 3 Registers
NAME ADDRESS RANGE SIZE ( × 16) Access Type
McBSP-A Registers 0x5000 - 0x503F 64
McBSP-B Registers 0x5040 - 0x507F 64
EPWM1 + HRPWM1 (DMA)
(1)
0x5800 - 0x583F 64
EPWM2 + HRPWM2 (DMA) 0x5840 - 0x587F 64
EPWM3 + HRPWM3 (DMA) 0x5880 - 0x58BF 64
EPWM4 + HRPWM4 (DMA) 0x58C0 - 0x58FF 64
EPWM5 + HRPWM5 (DMA) 0x5900 - 0x593F 64
EPWM6 + HRPWM6 (DMA) 0x5940 - 0x597F 64
(1)
The ePWM/HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To
achieve this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected.
When this bit is 0, the ePWM/HRPWM modules are mapped to Peripheral Frame 1.
SPRUFB0C – September 2007 – Revised May 2009 Peripheral Frames 111
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