External Interrupt Control Registers
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Table 6-18. External Interrupt 2 Counter (XINT2CTR) Field Descriptions
Bits Field Description
15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is
reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid
interrupt edge is detected. When the interrupt is disabled, the counter stops. The counter is a free-running
counter and wraps around to zero when the max value is reached. The counter is a read only register and
can only be reset to zero by a valid interrupt edge or by reset.
Figure 6-18. External NMI Interrupt Counter (XNMICTR) (Address 707Fh)
15 0
INTCTR[15-0]
R-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-19. External NMI Interrupt Counter (XNMICTR) Field Descriptions
Bits Field Description
15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is
reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid
interrupt edge is detected. When the interrupt is disabled, the counter stops. The counter is a free-running
counter and wraps around to zero when the max value is reached. The counter is a read only register and
can only be reset to zero by a valid interrupt edge or by reset.
150 Peripheral Interrupt Expansion (PIE) SPRUFB0C – September 2007 – Revised May 2009
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