GPBDAT
(latch)
GPBCLEAR
GPBTOGGLE
GPBSEL1
Qual
GPBMUX1
SYSCLKOUT
High
Impedance
Output
Control
GPIO32,
GPIO33
Pins
PU
XRS
0
=
Input
,
1
=
Output
Sync
GPBDIR
(latch)
01
11
01
GPBCTRL
2
2
10
Perpheralî˜ 1î˜ input
N/C
(defaultî˜ onî˜ reset)
GPIO32/33_OUT
(defaultî˜ onî˜ reset)
GPBPUD
0 = enableî˜ PU
1 = disableî˜ PU
(disabledî˜ afterî˜ reset)
async
(asyncî˜ disable
whenî˜ low)
0x
1x
11
10
Peripheralî˜ 2î˜ input
Peripheralî˜ 3î˜ input
GPBSET
(defaultî˜ onî˜ reset)
3î˜ samples
6î˜ samples
00
00
XRS
Defaultî˜ atî˜ Reset
External
interrupt
MUX
GPIOî˜ XINT6SEL
GPIOî˜ XINT7SEL
GPIOî˜ XINT5SEL
GPIOî˜ XINT4SEL
GPIOî˜ XINT3SEL
PIE
GPBDAT (read)
01
Perpheralî˜ 1î˜ output
11
10
Peripheralî˜ 2î˜ output
Peripheralî˜ 3î˜ output
00
01
11
10 Peripheralî˜ 2î˜ outputî˜ enable
Peripheralî˜ 3î˜ outputî˜ enable
00
SDAA/SCLA (I2Cî˜ outputî˜ enable)
SDAA/SCLA (I2Cî˜ dataî˜ out)
GPIO32/33-DIR
GPIO Module Overview
www.ti.com
Figure 4-3. GPIO32, GPIO33 Multiplexing Diagram
A The GPIOINENCLK bit in the PCLKCR3 register does not affect the above GPIOs (I2C pins) since the pins are
bi-directional.
B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode).
Any state will get flushed by the circuit eventually.
General-Purpose Input/Output (GPIO)68 SPRUFB0C – September 2007 – Revised May 2009
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