3.2.5 PLL Control, Status and XCLKOUT Register Descriptions
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OSC and PLL Block
The DIV field in the PLLCR register controls whether the PLL is bypassed or not and sets the PLL
clocking ratio when it is not bypassed. PLL bypass is the default mode after reset. Do not write to the DIV
field if the PLLSTS[DIVSEL] bit is 10 or 01, or if the PLL is operating in limp mode as indicated by the
PLLSTS[MCLKSTS] bit being set. See the procedure for changing the PLLCR described in Figure 3-10 .
Figure 3-11. PLLCR Register Layout
15 4 3 0
Reserved DIV
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-8. PLLCR Bit Descriptions
(1)
SYSCLKOUT (CLKIN)
(2)
PLLCR[DIV] Value
(3)
PLLSTS[DIVSEL] = 0 or 1 PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
0000 (PLL bypass) OSCCLK/4 (Default) OSCCLK/2 OSCCLK
0001 (OSCCLK * 1)/4 (OSCCLK*1)/2 –
0010 (OSCCLK * 2)/4 (OSCCLK*2)/2 –
0011 (OSCCLK * 3)/4 (OSCCLK*3)/2 –
0100 (OSCCLK * 4)/4 (OSCCLK*4)/2 –
0101 (OSCCLK * 5)/4 (OSCCLK*5)/2 –
0110 (OSCCLK * 6)/4 (OSCCLK*6)/2 –
0111 (OSCCLK * 7)/4 (OSCCLK*7)/2 –
1000 (OSCCLK * 8)/4 (OSCCLK*8)/2 –
1001 (OSCCLK * 9)/4 (OSCCLK*9)/2 –
1010 (OSCCLK * 10)/4 (OSCCLK*10)/2 –
1011 - 1111 Reserved Reserved Reserved
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. See
Figure 3-10 .
(3)
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a
watchdog reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
Figure 3-12. PLL Status Register (PLLSTS)
15 9 8
Reserved DIVSEL
R-0 R/W-0
7 6 5 4 3 2 1 0
DIVSEL MCLKOFF OSCOFF MCLKCLR MCLKSTS PLLOFF Reserved PLLLOCKS
R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-9. PLL Status Register (PLLSTS) Field Descriptions
Bits Field Value Description
(1) (2)
15-9 Reserved Reserved
8:7 DIVSEL Divide Select: This bit selects between /4, /2, and /1 for CLKIN to the CPU.
The configuration of the DIVSEL bit is as follows:
(1)
This register is reset to its default state only by the XRS signal or a watchdog reset. It is not reset by a missing clock or debugger reset.
(2)
This register is EALLOW protected. See Section 5.2 for more information.
SPRUFB0C – September 2007 – Revised May 2009 Clocking 51
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