6.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts
Interrupt Sources
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The proper procedure for enabling or disabling an interrupt is by using the peripheral interrupt
enable/disable flags. The primary purpose of the PIEIER and CPU IER registers is for software
prioritization of interrupts within the same PIE interrupt group. The software package C280x C/C++
Header Files and Peripheral Examples in C (literature number SPRC530 ) includes an example that
illustrates this method of software prioritizing interrupts.
Should bits within the PIEIER registers need to be cleared outside of this context, one of the following two
procedures should be followed. The first method preserves the associated PIE flag register so that
interrupts are not lost. The second method clears the associated PIE flag register.
Method 1: Use the PIEIERx register to disable the interrupt and preserve the associated PIEIFRx
flags.
To clear bits within a PIEIERx register while preserving the associated flags in the PIEIFRx register, the
following procedure should be followed:
Step a. Disable global interrupts (INTM = 1).
Step b. Clear the PIEIERx.y bit to disable the interrupt for a given peripheral. This can be done for
one or more peripherals within the same group.
Step c. Wait 5 cycles. This delay is required to be sure that any interrupt that was incoming to the
CPU has been flagged within the CPU IFR register.
Step d. Clear the CPU IFRx bit for the peripheral group. This is a safe operation on the CPU IFR
register.
Step e. Clear the PIEACKx bit for the peripheral group.
Step f. Enable global interrupts (INTM = 0).
Method 2: Use the PIEIERx register to disable the interrupt and clear the associated PIEIFRx flags.
To perform a software reset of a peripheral interrupt and clear the associated flag in the PIEIFRx register
and CPU IFR register, the following procedure should be followed:
Step 1. Disable global interrupts (INTM = 1).
Step 2. Set the EALLOW bit.
Step 3. Modify the PIE vector table to temporarily map the vector of the specific peripheral interrupt to
a empty interrupt service routine (ISR). This empty ISR will only perform a return from
interrupt (IRET) instruction. This is the safe way to clear a single PIEIFRx.y bit without losing
any interrupts from other peripherals within the group.
Step 4. Disable the peripheral interrupt at the peripheral register.
Step 5. Enable global interrupts (INTM = 0).
Step 6. Wait for any pending interrupt from the peripheral to be serviced by the empty ISR routine.
Step 7. Disable global interrupts (INTM = 1).
Step 8. Modify the PIE vector table to map the peripheral vector back to its original ISR.
Step 9. Clear the EALLOW bit.
Step 10. Disable the PIEIER bit for given peripheral.
Step 11. Clear the IFR bit for given peripheral group (this is safe operation on CPU IFR register).
Step 12. Clear the PIEACK bit for the PIE group.
Step 13. Enable global interrupts.
130 Peripheral Interrupt Expansion (PIE) SPRUFB0C – September 2007 – Revised May 2009
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