5.2 EALLOW-Protected Registers
EALLOW-Protected Registers
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Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism.
The EALLOW bit in status register 1 (ST1) indicates if the state of protection as shown in Table 5-5 .
Table 5-5. Access to EALLOW-Protected Registers
EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed Allowed
(1)
Allowed
1 Allowed Allowed Allowed Allowed
(1)
The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio interface.
At reset the EALLOW bit is cleared enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this
bit is set, by executing the EALLOW instruction, then the CPU is allowed to write freely to protected
registers. After modifying registers, they can once again be protected by executing the EDI instruction to
clear the EALLOW bit.
The following registers are EALLOW-protected:
• Device Emulation Registers
• Flash Registers
• CSM Registers
• PIE Vector Table
• System Control Registers
• GPIO MUX Registers
• Certain eCAN Registers
• XINTF Registers
Table 5-6. EALLOW-Protected Device Emulation Registers
Name Address Size Description
(x16)
DEVICECNF 0x0880 2 Device Configuration Register
0x0881
PROTSTART 0x0884 1 Block Protection Start Address Register
PROTRANGE 0x0885 1 Block Protection Range Address Register
Table 5-7. EALLOW-Protected Flash/OTP Configuration Registers
Size
Name Address (x16) Description
FOPT 0x0A80 1 Flash Option Register
FPWR 0x0A82 1 Flash Power Modes Register
FSTATUS 0x0A83 1 Status Register
FSTDBYWAIT 0x0A84 1 Flash Sleep To Standby Wait State Register
FACTIVEWAIT 0x0A85 1 Flash Standby To Active Wait State Register
FBANKWAIT 0x0A86 1 Flash Read Access Wait State Register
FOTPWAIT 0x0A87 1 OTP Read Access Wait State Register
Peripheral Frames112 SPRUFB0C – September 2007 – Revised May 2009
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