3.4.3 Watchdog Operation in Low Power Modes
3.4.4 Emulation Considerations
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Watchdog Block
In STANDBY mode, all of the clocks to the peripherals are turned off on the device. The only peripheral
that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake
the device from STANDBY low power mode (if enabled). See the Low Power Modes Block section of the
device data manual for details.
In IDLE mode, the watchdog interrupt ( WDINT) signal can generate an interrupt to the CPU to take the
CPU out of IDLE mode. The watchdog is connected to the WAKEINT interrupt in the PIE.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode
condition, then make sure that the WDINT signal goes back high again before attempting to
go back into the IDLE or STANDBY mode. The WDINT signal will be held low for 512
OSCCLK cycles when the watchdog interrupt is generated. You can determine the current
state of WDINT by reading the watchdog interrupt status bit (WDINTS) bit in the SCSR
register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and, therefore,
so is the watchdog.
The watchdog module behaves as follows under various debug conditions:
CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is suspended
Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step When the CPU is in real-time single-step mode, the watchdog clock
Mode: (WDCLK) is suspended. The watchdog remains suspended even within
real-time interrupts.
Real-Time Run-Free When the CPU is in real-time run-free mode, the watchdog operates as
Mode: normal.
SPRUFB0C – September 2007 – Revised May 2009 Clocking 57
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