3.2.6 External Reference Oscillator Clock Option
OSC and PLL Block
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Table 3-9. PLL Status Register (PLLSTS) Field Descriptions (continued)
Bits Field Value Description
(1) (2)
00 Select Divide By 8 for CLKIN
00, 01 Select Divide By 4 for CLKIN
10 Select Divide By 2 for CLKIN
11 Select Divide By 1 for CLKIN . (This mode can be used only when PLL is off or bypassed.)
6 MCLKOFF Missing clock-detect off bit
0 Main oscillator fail-detect logic is enabled. (default)
1 Main oscillator fail-detect logic is disabled and the PLL will not issue a limp-mode clock. Use this
mode when code must not be affected by the detection circuit. For example, if external clocks are
turned off.
5 OSCOFF Oscillator Clock Off Bit
0 The OSCCLK signal from X1, X1/X2 or XCLKIN is fed to the PLL block. (default)
1 The OSCCLK signal from X1, X1/X2 or XCLKIN is not fed to the PLL block. This does not shut
down the internal oscillator. The OSCOFF bit is used for testing the missing clock detection logic.
When the OSCOFF bit is set, do not enter HALT or STANDBY modes or write to PLLCR as these
operations can result in unpredictable behavior.
When the OSCOFF bit is set, the behavior of the watchdog is different depending on which input
clock source (X1, X1/X2 or XCLKIN) is being used:
• X1 or X1/X2: The watchdog is not functional.
• XCLKIN: The watchdog is functional and should be disabled before setting OSCOFF.
4 MCLKCLR Missing Clock Clear Bit.
0 Writing a 0 has no effect. This bit always reads 0.
1 Forces the missing clock detection circuits to be cleared and reset. If OSCCLK is still missing, the
detection circuit will again generate a reset to the system, set the missing clock status bit
(MCLKSTS), and the CPU will be powered by the PLL operating at a "limp mode" frequency.
3 MCLKSTS Missing Clock Status Bit. Check the status of this bit after a reset to determine whether a missing
oscillator condition was detected. Under normal conditions, this bit should be 0. Writes to this bit
are ignored. This bit will be cleared by writing to the MCLKCLR bit or by forcing an external reset.
0 Indicates normal operation. A missing clock condition has not been detected.
1 Indicates that OSCCLK was detected as missing. The main oscillator fail detect logic has reset the
device and the CPU is now clocked by the PLL operating at the limp mode frequency.
2 PLLOFF PLL Off Bit. This bit turns off the PLL. This is useful for system noise testing. This mode must only
be used when the PLLCR register is set to 0x0000.
0 PLL On (default)
1 PLL Off. While the PLLOFF bit is set the PLL module will be kept powered down.
The device must be in PLL bypass mode (PLLCR = 0x0000) before writing a 1 to PLLOFF. While
the PLL is turned off (PLLOFF = 1), do not write a non-zero value to the PLLCR.
The STANDBY and HALT low power modes will work as expected when PLLOFF = 1. After waking
up from HALT or STANDBY the PLL module will remain powered down.
1 Reserved Reserved
0 PLLLOCKS PLL Lock Status Bit.
0 Indicates that the PLLCR register has been written to and the PLL is currently locking. The CPU is
clocked by OSCCLK/2 until the PLL locks.
1 Indicates that the PLL has finished locking and is now stable.
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values to provide
proper start-up and stability over the entire operating range.
Clocking52 SPRUFB0C – September 2007 – Revised May 2009
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