Chapter 6
SPRUFB0C – September 2007 – Revised May 2009
Peripheral Interrupt Expansion (PIE)
The peripheral interrupt expansion (PIE) block multiplexes numerous interrupt sources into a smaller set of
interrupt inputs. The PIE block can support 96 individual interrupts that are grouped into blocks of eight.
Each group is fed into one of 12 core interrupt lines (INT1 to INT12). Each of the 96 interrupts is
supported by its own vector stored in a dedicated RAM block that you can modify. The CPU, upon
servicing the interrupt, automatically fetches the appropriate interrupt vector. It takes nine CPU clock
cycles to fetch the vector and save critical CPU registers. Therefore, the CPU can respond quickly to
interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt
can be enabled/disabled within the PIE block.
Topic .................................................................................................. Page
6.1 Overview of the PIE Controller .................................................. 122
6.2 Vector Table Mapping .............................................................. 125
6.3 Interrupt Sources .................................................................... 127
6.4 PIE Configuration Registers ..................................................... 139
6.5 PIE Interrupt Registers ............................................................. 140
6.6 External Interrupt Control Registers ......................................... 148
SPRUFB0C – September 2007 – Revised May 2009 Peripheral Interrupt Expansion (PIE) 121
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