Texas Instruments TMS320x2833 series User Manual

4.2 Configuration Overview
www.ti.com Configuration Overview
The pin function assignments, input qualification, and the external interrupt (XINT1 – XINT7, XNMI)
sources are all controlled by the GPIO configuration control registers. In addition, you can assign pins to
wake the device from the HALT and STANDBY low power modes and enable/disable internal pullup
resistors. Table 4-1 and Table 4-2 list the registers that are used to configure the GPIO pins to match the
system requirements.
Table 4-1. GPIO Control Registers
Name
(1)
Address Size (x16) Register Description Bit Description
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0-GPIO31) Figure 4-14
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0-GPIO15) Figure 4-16
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16-GPIO31) Figure 4-17
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0-GPIO15) Figure 4-8
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16-GPIO31) Figure 4-9
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0-GPIO31) Figure 4-20
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0-GPIO31) Figure 4-23
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32-GPIO63) Figure 4-15
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32-GPIO47) Figure 4-18
GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register (GPIO48 - GPIO63) Figure 4-19
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32-GPIO47) Figure 4-10
GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48-GPIO63) Figure 4-11
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32-GPIO63) Figure 4-21
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32-GPIO63) Figure 4-24
GPCMUX1 0x6FA6 2 GPIO C MUX 1 Register (GPIO64-GPIO79) Figure 4-12
GPCMUX2 0x6FA8 2 GPIO C MUX 2 Register (GPIO80-GPIO87) Figure 4-13
GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64-GPIO87) Figure 4-22
GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64-GPIO87) Figure 4-25
(1)
The registers in this table are EALLOW protected. See Section 5.2 for more information.
Table 4-2. GPIO Interrupt and Low Power Mode Select Registers
Size
Name
(1)
Address Register Description Bit Description
(x16)
GPIOXINT1SEL 0x6FE0 1 XINT1 Source Select Register (GPIO0-GPIO31) Figure 4-32
GPIOXINT2SEL 0x6FE1 1 XINT2 Source Select Register (GPIO0-GPIO31) Figure 4-32
GPIOXNMISEL 0x6FE2 1 XNMI Source Select Register (GPIO0-GPIO31) Figure 4-32
GPIOXINT3SEL 0x6FE3 1 XINT3 Source Select Register (GPIO32 - GPIO63) Table 4-44
GPIOXINT4SEL 0x6FE4 1 XINT4 Source Select Register (GPIO32 - GPIO63) Table 4-44
GPIOXINT5SEL 0x6FE5 1 XINT5 Source Select Register (GPIO32 - GPIO63) Table 4-44
GPIOXINT6SEL 0x6FE6 1 XINT6 Source Select Register (GPIO32 - GPIO63) Table 4-44
GPIOXINT7SEL 0x6FE7 1 XINT7 Source Select Register (GPIO32 - GPIO63) Table 4-44
GPIOLPMSEL 0x6FE8 1 LPM wakeup Source Select Register (GPIO0-GPIO31) Figure 4-33
(1)
The registers in this table are EALLOW protected. See Section 5.2 for more information.
SPRUFB0C – September 2007 – Revised May 2009 General-Purpose Input/Output (GPIO) 71
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Texas Instruments TMS320x2833 series Specifications

General

Brand	Texas Instruments
Model	TMS320x2833 series
Category	Controller
Language	English