Texas Instruments TMS320x2833 series User Manual

Contents
Preface .............................................................................................................................. 11
1 Flash and OTP Memory Blocks .................................................................................. 15
1.1 Flash and OTP Memory ................................................................................................... 16
1.1.1 Flash Memory ...................................................................................................... 16
1.1.2 OTP Memory ....................................................................................................... 16
1.2 Flash and OTP Power Modes ............................................................................................ 16
1.2.1 Flash and OTP Performance ................................................................................... 18
1.2.2 Flash Pipeline Mode .............................................................................................. 18
1.2.3 Reserved Locations Within Flash and OTP ................................................................... 19
1.2.4 Procedure to Change the Flash Configuration Registers .................................................... 20
1.3 Flash and OTP Registers ................................................................................................. 21
2 Code Security Module (CSM) ..................................................................................... 27
2.1 Functional Description ..................................................................................................... 28
2.2 CSM Impact on Other On-Chip Resources ............................................................................. 30
2.3 Incorporating Code Security in User Applications ..................................................................... 31
2.3.1 Environments That Require Security Unlocking .............................................................. 32
2.3.2 Password Match Flow ........................................................................................... 33
2.3.3 Unsecuring Considerations for Devices With/Without Code Security ...................................... 34
2.4 Do's and Don'ts to Protect Security Logic ............................................................................... 36
2.4.1 Do's ................................................................................................................. 36
2.4.2 Don'ts .............................................................................................................. 36
2.5 CSM Features - Summary ................................................................................................ 36
3 Clocking .................................................................................................................. 37
3.1 Clocking and System Control ............................................................................................. 38
3.2 OSC and PLL Block ........................................................................................................ 45
3.2.1 PLL-Based Clock Module ........................................................................................ 45
3.2.2 Main Oscillator Fail Detection.................................................................................... 46
3.2.3 XCLKOUT Generation ............................................................................................ 48
3.2.4 PLL Control (PLLCR) Register .................................................................................. 49
3.2.5 PLL Control, Status and XCLKOUT Register Descriptions .................................................. 51
3.2.6 External Reference Oscillator Clock Option ................................................................... 52
3.3 Low-Power Modes Block .................................................................................................. 53
3.4 Watchdog Block ............................................................................................................ 55
3.4.1 Servicing The Watchdog Timer .................................................................................. 56
3.4.2 Watchdog Reset or Watchdog Interrupt Mode ................................................................ 56
3.4.3 Watchdog Operation in Low Power Modes .................................................................... 57
3.4.4 Emulation Considerations ........................................................................................ 57
3.4.5 Watchdog Registers .............................................................................................. 58
3.5 32-Bit CPU Timers 0/1/2 .................................................................................................. 60
4 General-Purpose Input/Output (GPIO) ......................................................................... 65
SPRUFB0C – September 2007 – Revised May 2009 Contents 3
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Texas Instruments TMS320x2833 series Specifications

General

Brand	Texas Instruments
Model	TMS320x2833 series
Category	Controller
Language	English