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4.1 GPIO Module Overview ................................................................................................... 66
4.2 Configuration Overview .................................................................................................... 71
4.3 Digital General Purpose I/O Control ..................................................................................... 72
4.4 Input Qualification .......................................................................................................... 74
4.4.1 No Synchronization (asynchronous input) ..................................................................... 74
4.4.2 Synchronization to SYSCLKOUT Only ......................................................................... 74
4.4.3 Qualification Using a Sampling Window ....................................................................... 74
4.5 GPIO and Peripheral Multiplexing (MUX) ............................................................................... 78
4.6 Register Bit Definitions .................................................................................................... 83
5 Peripheral Frames ................................................................................................... 109
5.1 Peripheral Frame Registers ............................................................................................. 110
5.2 EALLOW-Protected Registers .......................................................................................... 112
5.3 Device Emulation Registers ............................................................................................. 116
5.4 Write-Followed-by-Read Protection .................................................................................... 118
6 Peripheral Interrupt Expansion (PIE) ......................................................................... 121
6.1 Overview of the PIE Controller .......................................................................................... 122
6.1.1 Interrupt Operation Sequence .................................................................................. 122
6.2 Vector Table Mapping .................................................................................................... 125
6.3 Interrupt Sources.......................................................................................................... 127
6.3.1 Procedure for Handling Multiplexed Interrupts ............................................................... 129
6.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts ............................... 130
6.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU ................................. 131
6.3.4 The PIE Vector Table ........................................................................................... 132
6.4 PIE Configuration Registers ............................................................................................. 139
6.5 PIE Interrupt Registers ................................................................................................... 140
6.5.1 PIE Interrupt Flag Registers .................................................................................... 141
6.5.2 PIE Interrupt Enable Registers ................................................................................. 141
6.5.3 CPU Interrupt Flag Register (IFR) ............................................................................. 142
6.5.4 Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER) ...................... 144
6.6 External Interrupt Control Registers ................................................................................... 148
A Revision History ..................................................................................................... 151
Contents 4 SPRUFB0C – September 2007 – Revised May 2009
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