Flash and OTP Registers
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Figure 1-10. OTP Wait-State Register (FOTPWAIT)
15 5 4 0
Reserved OTPWAIT
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions
Bit(s) Field Value Description
(1) (2) (3)
15-5 Reserved 0 Reserved
4-0 OTPWAIT OTP Read Wait States. These register bits specify the number of wait states for a read operation in
CPU clock cycles (1..31 SYSCLKOUT cycles) to the OTP. See CPU Read Or Fetch Access From
flash/OTP section for details. There is no PAGE mode in the OTP.
OTPWAIT must be set greater than 0. That is, a minimum of 1 wait state must be used. See the
device-specific data manual for the minimum time required for an OTP access.
00000 Illegal value. OTPWAIT must be set to 1 or greater.
00001 One wait state will be used each OTP access for a total of two SYSCLKOUT cycles per access.
00010 Two wait states will be used for each OTP access for a total of three SYSCLKOUT cycles per access.
00011 Three wait states will be used for each OTP access for a total of four SYSCLKOUT cycles per access.
. . . . . .
11111 31 wait states will be used for an OTP access for a total of 32 SYSCLKOUT cycles per access.
(1)
This register is EALLOW protected. See Section 5.2 for more information.
(2)
This register is protected by the Code Security Module (CSM). See Chapter 2 for more information.
(3)
When writing to this register, follow the procedure described in Section 1.2.4 .
26 Flash and OTP Memory Blocks SPRUFB0C – September 2007 – Revised May 2009
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