Texas Instruments TMS320x2833 series

4.1 GPIO Module Overview
GPADAT
(latch)
GPACLEAR,
GPATOGGLE
GPAQSEL 1/2
Qual
GPAMUX 1/2
SYSCLKOUT
High
impedance
output
control
GPIO0
to
GPIO27
Pins
PU
XRS
Sync
Lowpower
modesblock
GPIOx.async
GPADIR
(latch)
01
11
01
GPACTRL
2
2
10
Peripheral1input
N/C
(defaultonreset)
(defaultonreset)
GPIOx_OUT
GPIOx_DIR
GPAPUD
0 = enablePU
1 = disablePU
(disabledafterreset)
async
(asyncdisable
whenlow)
11
10
Peripheral2input
Peripheral3input
Peripheral1output
GPASET,
(default
onreset)
3samples
6samples
00
00
XRS
(defaultonreset)
01
11
10
00
01
11
10
00
0=input,1=output
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
External
interrupt
MUX
PIE
GPADAT (read)
GPIOLPMSEL
LPMCR0
Peripheral2output
Peripheral3output
Peripheral1outputenable
Peripheral2outputenable
Peripheral3outputenable
GPIO Module Overview www.ti.com
Up to three independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to
individual pin bit-I/O capability. There are three 32-bit I/O ports. Port A consists of GPIO0-GPIO31, port B
consists of GPIO32-GPIO63, and port C consists of GPIO64-87. Figure 4-1 shows the basic modes of
operation for the GPIO module.
Figure 4-1. GPIO0 to GPIO27 Multiplexing Diagram
A GPxDAT latch/read are accessed at the same memory location.
66 General-Purpose Input/Output (GPIO) SPRUFB0C – September 2007 – Revised May 2009
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