4.1 GPIO Module Overview
GPADAT
(latch)
GPACLEAR,
GPATOGGLE
GPAQSEL 1/2
Qual
GPAMUX 1/2
SYSCLKOUT
High
impedance
output
control
GPIO0
to
GPIO27
Pins
PU
XRS
Sync
Lowî˜ power
modesî˜ block
GPIOx.async
GPADIR
(latch)
01
11
01
GPACTRL
2
2
10
Peripheralî˜ 1î˜ input
N/C
(defaultî˜ onî˜ reset)
(defaultî˜ onî˜ reset)
GPIOx_OUT
GPIOx_DIR
GPAPUD
0 = enableî˜ PU
1 = disableî˜ PU
(disabledî˜ afterî˜ reset)
async
(asyncî˜ disable
whenî˜ low)
11
10
Peripheralî˜ 2î˜ input
Peripheralî˜ 3î˜ input
Peripheralî˜ 1î˜ output
GPASET,
(default
onî˜ reset)
3î˜ samples
6î˜ samples
00
00
XRS
(defaultî˜ onî˜ reset)
01
11
10
00
01
11
10
00
0î˜ =î˜ input,î˜ 1î˜ =î˜ output
GPIOî˜ XINT1SEL
GPIOî˜ XINT2SEL
GPIOXNMISEL
External
interrupt
MUX
PIE
GPADAT (read)
GPIOLPMSEL
LPMCR0
Peripheralî˜ 2î˜ output
Peripheralî˜ 3î˜ output
Peripheralî˜ 1î˜ outputî˜ enable
Peripheralî˜ 2î˜ outputî˜ enable
Peripheralî˜ 3î˜ outputî˜ enable
GPIO Module Overview
www.ti.com
Up to three independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to
individual pin bit-I/O capability. There are three 32-bit I/O ports. Port A consists of GPIO0-GPIO31, port B
consists of GPIO32-GPIO63, and port C consists of GPIO64-87. Figure 4-1 shows the basic modes of
operation for the GPIO module.
Figure 4-1. GPIO0 to GPIO27 Multiplexing Diagram
A GPxDAT latch/read are accessed at the same memory location.
66 General-Purpose Input/Output (GPIO) SPRUFB0C – September 2007 – Revised May 2009
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