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List of Figures
1-1 Flash Power Mode State Diagram ....................................................................................... 17
1-2 Flash Pipeline ............................................................................................................... 19
1-3 Flash Configuration Access Flow Diagram ............................................................................. 20
1-4 Flash Options Register (FOPT) .......................................................................................... 22
1-5 Flash Power Register (FPWR) ........................................................................................... 22
1-6 Flash Status Register (FSTATUS) ....................................................................................... 23
1-7 Flash Standby Wait Register (FSTDBYWAIT) ......................................................................... 24
1-8 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) .................................................. 24
1-9 Flash Wait-State Register (FBANKWAIT) .............................................................................. 25
1-10 OTP Wait-State Register (FOTPWAIT) ................................................................................. 26
2-1 CSM Status and Control Register (CSMSCR) ......................................................................... 32
2-2 Password Match Flow (PMF) ............................................................................................ 33
3-1 Clock and Reset Domains ................................................................................................ 38
3-2 Peripheral Clock Control 0 Register (PCLKCR0) ...................................................................... 39
3-3 Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 40
3-4 Peripheral Clock Control 3 Register (PCLKCR3) ...................................................................... 43
3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Register ......................................................... 44
3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) ......................................................... 44
3-7 OSC and PLL Block ........................................................................................................ 45
3-8 Oscillator Fail-Detection Logic Diagram ................................................................................. 46
3-9 XCLKOUT Generation ..................................................................................................... 48
3-10 PLLCR Change Procedure Flow Chart .................................................................................. 50
3-11 PLLCR Register Layout ................................................................................................... 51
3-12 PLL Status Register (PLLSTS) ........................................................................................... 51
3-13 Low Power Mode Control 0 Register (LPMCR0) ....................................................................... 54
3-14 Watchdog Module .......................................................................................................... 55
3-15 System Control and Status Register (SCSR) .......................................................................... 58
3-16 Watchdog Counter Register (WDCNTR) ................................................................................ 59
3-17 Watchdog Reset Key Register (WDKEY) ............................................................................... 59
3-18 Watchdog Control Register (WDCR) .................................................................................... 59
3-19 CPU-Timers ................................................................................................................. 60
3-20 CPU-Timer Interrupts Signals and Output Signal ...................................................................... 61
3-21 TIMERxTIM Register (x = 0, 1, 2) ........................................................................................ 62
3-22 TIMERxTIMH Register (x = 0, 1, 2) ...................................................................................... 62
3-23 TIMERxPRD Register (x = 0, 1, 2) ....................................................................................... 62
3-24 TIMERxPRDH Register (x = 0, 1, 2) ..................................................................................... 62
3-25 TIMERxTCR Register (x = 0, 1, 2) ....................................................................................... 63
3-26 TIMERxTPR Register (x = 0, 1, 2) ....................................................................................... 64
3-27 TIMERxTPRH Register (x = 0, 1, 2) .................................................................................... 64
4-1 GPIO0 to GPIO27 Multiplexing Diagram ................................................................................ 66
4-2 GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 67
4-3 GPIO32, GPIO33 Multiplexing Diagram ................................................................................. 68
4-4 GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 69
4-5 GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification) ................................ 70
4-6 Input Qualification Using a Sampling Window .......................................................................... 74
4-7 Input Qualifier Clock Cycles .............................................................................................. 77
4-8 GPIO Port A MUX 1 (GPAMUX1) Register ............................................................................. 83
4-9 GPIO Port A MUX 2 (GPAMUX2) Register ............................................................................. 85
4-10 GPIO Port B MUX 1 (GPBMUX1) Register ............................................................................. 87
4-11 GPIO Port B MUX 2 (GPBMUX2) Register ............................................................................. 89
4-12 GPIO Port C MUX 1 (GPCMUX1) Register ............................................................................. 91
4-13 GPIO Port C MUX 2 (GPCMUX2) Register ............................................................................. 92
SPRUFB0C – September 2007 – Revised May 2009 List of Figures 5
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