3.3 Low-Power Modes Block
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Low-Power Modes Block
Table 3-10 summarizes the various modes.
The various low-power modes operate as shown in Table 3-11 .
See the TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234,
TMS320F28232 Digital Signal Controllers (DSCs) Data Manual (literature number SPRS439 ) for exact
timing for entering and exiting the low power modes.
Table 3-10. Low-Power Mode Summary
Mode LPMCR0[1:0] OSCCLK CLKIN SYSCLKOUT Exit
(1)
IDLE 00 On On On
(2)
XRS,
Watchdog interrupt,
Any enabled interrupt
STANDBY 01 On Off Off XRS,
(watchdog still running) Watchdog interrupt,
GPIO Port A signal,
Debugger
(3)
HALT 1X Off Off Off XRS,
(oscillator and PLL turned off, GPIO Port A Signal,
watchdog not functional) Debugger
(3)
(1)
The Exit column lists which signals or under what conditions the low power mode is exited. This signal must be kept low long
enough for an interrupt to be recognized by the device. Otherwise the IDLE mode is not exited and the device goes back into
the indicated low power mode.
(2)
The IDLE mode on the 28x behaves differently than on the 24x/240x. On the 28x, the clock output from the CPU
(SYSCLKOUT) is still functional while on the 24x/240x the clock is turned off.
(3)
On the 28x, the JTAG port can still function even if the clock to the CPU (CLKIN) is turned off.
Table 3-11. Low Power Modes
Mode Description
IDLE This mode is exited by any enabled interrupt or an NMI. The LPM block itself performs no tasks during this
Mode: mode.
STANDBY If the LPM bits in the LPMCR0 register are set to 01, the device enters STANDBY mode when the IDLE
Mode: instruction is executed. In STANDBY mode the clock input to the CPU (CLKIN) is disabled, which disables all
clocks derived from SYSCLKOUT. The oscillator and PLL and watchdog will still function. Before entering the
STANDBY mode, you should perform the following tasks:
• Enable the WAKEINT interrupt in the PIE module. This interrupt is connected to both the watchdog and the
low power mode module interrupt.
• If desired, specify one of the GPIO port A signals to wake the device in the GPIOLPMSEL register. The
GPIOLPMSEL register is part of the GPIO module. In addition to the selected GPIO signal, the XRS input
and the watchdog interrupt, if enabled in the LPMCR0 register, can wake the device from the STANDBY
mode.
• Select the input qualification in the LPMCR0 register for the signal that will wake the device.
When the selected external signal goes low, it must remain low a number of OSCCLK cycles as specified by the
qualification period in the LPMCR0 register. If the signal should be sampled high during this time, the
qualification will restart. At the end of the qualification period, the PLL enables the CLKIN to the CPU and the
WAKEINT interrupt is latched in the PIE block. The CPU then responds to the WAKEINT interrupt if it is enabled.
SPRUFB0C – September 2007 – Revised May 2009 Clocking 53
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