GPADAT
(latch)
GPACLEAR
GPATOGGLE
GPAQSEL 1/2
Qual
GPAMUX 1/2
SYSCLKOUT
High-
Impedance
Output
Control
GPIO28,
GPIO29,
GPIO30,
GPIO31
Pins
PU
XRS
0 = Input , 1 = Output
Sync
Lowî˜ Power
Modesî˜ Block
GPIOx.async
GPADIR
(latch)
01
11
01
01
0x
1x
01
GPACTRL
2
2
10
Perpheralî˜ 1î˜ input
N/C
(defaultî˜ onî˜ reset)
(defaultî˜ onî˜ reset)
GPIOx_OUT
GPIOx_DIR
GPAPUD
0 = enableî˜ PU
1 = disableî˜ PU
(disabledî˜ afterî˜ reset)
async
(asyncî˜ disable
whenî˜ low)
0x
1x
11
10
XINTFî˜ Outputî˜ Signals
XZCS6,î˜ XA19,î˜ XA18,î˜ XA17
1
N/C
N/C
Perpheralî˜ 1î˜ output
Perpheralî˜ 1î˜ ouputî˜ enable
GPASET
(defaultî˜ onî˜ reset)
3î˜ samples
6î˜ samples
LPMCR0
GPIOLPMSEL
00
00
00
00
XRS
Defaultî˜ atî˜ Reset
External
interrupt
MUX
GPIOî˜ XINT2SEL
GPIOXNMISEL
GPIOî˜ XINT1SEL
PIE
GPADAT (read)
www.ti.com
GPIO Module Overview
Figure 4-2. GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged)
A The shaded area is disabled in the above GPIOs when the GPIOINENCLK bit is cleared to 0 in the PCLKCR3
register and the respective pin is configured as an output. This is to reduce power consumption when a pin is
configured as an output. Clearing the GPIOINCLK bit will reset the sync and qualification logic so no residual value is
left.
B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode).
Any state will get flushed by the circuit eventually.
SPRUFB0C – September 2007 – Revised May 2009 General-Purpose Input/Output (GPIO) 67
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