Texas Instruments TMS320x2833 series User Manual

2.3.3 Unsecuring Considerations for Devices With/Without Code Security
Incorporating Code Security in User Applications www.ti.com
Case 1 and Case 2 provide unsecuring considerations for devices with and without code security.
Case 1: Device With Code Security
A device with code security should have a predetermined password stored in the password locations
(0x33 FFF8 - 0x33 FFFF in memory). In addition, locations 0x33 FF80 - 0x33 FFF5 should be
programmed with all 0x0000 and not used for program and/or data storage. The following are steps to
unsecure this device:
1. Perform a dummy read of the password locations.
2. Write the password into the KEY registers (locations 0x00 0AE0 - 0x00 0AE7 in memory).
3. If the password is correct, the device becomes unsecure; otherwise, it stays secure.
Case 2: Device Without Code Security
A device without code security should have 0x FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF (128 bits
of all ones) stored in the password locations. The following are steps to use this device:
1. At reset, the CSM will lock memory regions protected by the CSM.
2. Perform a dummy read of the password locations.
3. Since the password is all ones, this alone will unlock all memory regions. Secure memory is fully
accessible immediately after this operation is completed.
Note: Even if a device is not protected with a password (all password locations all ones), the CSM
will lock at reset. Thus, a dummy read operation must still be performed on these devices
prior to reading, writing, or programming secure memory if the code performing the access is
executing from outside of the CSM protected memory region. The Boot ROM code does this
dummy read for convenience.
34 Code Security Module (CSM) SPRUFB0C – September 2007 – Revised May 2009
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Texas Instruments TMS320x2833 series Specifications

General

Core	TMS320C28x
CPU Frequency (MHz)	150
Clock Speed	150 MHz
ADC Resolution (bits)	12
ADC Resolution	12-bit
Communication Interfaces	CAN, SPI, I2C, UART
CAN Modules	2
I2C Interfaces	1
Operating Temperature Range (°C)	-40 to 125
CPU Bit Size	32
Flash Memory (KB)	512
Number of ADC Channels	16
ADC Channels	16
PWM	16
UART Interfaces	2
Supply Voltage (V)	1.8, 3.3
Operating Voltage	1.8V, 3.3V

Summary

Chapter 1 Flash and OTP Memory Blocks

Flash and OTP Memory

Configures flash and one-time programmable (OTP) memory, its features, and power modes.

Flash and OTP Power Modes

Chapter 2 Code Security Module (CSM)

Functional Description

Explains the CSM's role in protecting on-chip memory access and security levels.

Incorporating Code Security in User Applications

Guides on setting up device security using passwords and key registers.

Chapter 3 Clocking

Clocking and System Control

Describes clock generation, system control, and reset domains.

OSC and PLL Block

Details the on-chip oscillator and PLL for clocking, including modes and fail detection.

Low-Power Modes Block

Watchdog Block

Chapter 4 General-Purpose Input/Output (GPIO)

GPIO Module Overview

Introduces the GPIO module, pin multiplexing, and I/O capabilities.

Configuration Overview

GPIO and Peripheral Multiplexing (MUX)

Chapter 6 Peripheral Interrupt Expansion (PIE)

Overview of the PIE Controller

Introduces the PIE controller for managing peripheral and external interrupts.

Interrupt Sources

Details various interrupt sources and their multiplexing within the PIE.

PIE Configuration Registers

PIE Interrupt Registers