Chapter 4
SPRUFB0C – September 2007 – Revised May 2009
General-Purpose Input/Output (GPIO)
The GPIO multiplexing (MUX) registers are used to select the operation of shared pins. The pins are
named by their general purpose I/O name (i.e., GPIO0 - GPIO87). These pins can be individually selected
to operate as digital I/O, referred to as GPIO, or connected to one of up to three peripheral I/O signals (via
the GPxMUXn registers). If selected for digital I/O mode, registers are provided to configure the pin
direction (via the GPxDIR registers). You can also qualify the input signals to remove unwanted noise (via
the GPxQSELn, GPACTRL, and GPBCTRL registers).
Topic .................................................................................................. Page
4.1 GPIO Module Overview .............................................................. 66
4.2 Configuration Overview ............................................................. 71
4.3 Digital General Purpose I/O Control ............................................ 72
4.4 Input Qualification ..................................................................... 74
4.5 GPIO and Peripheral Multiplexing (MUX) ...................................... 78
4.6 Register Bit Definitions .............................................................. 83
SPRUFB0C – September 2007 – Revised May 2009 General-Purpose Input/Output (GPIO) 65
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