2.1 Functional Description
Functional Description
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The security module restricts the CPU access to certain on-chip memory without interrupting or stalling
CPU execution. When a read occurs to a protected memory location, the read returns a zero value and
CPU execution continues with the next instruction. This, in effect, blocks read and write access to various
memories through the JTAG port or external peripherals. Security is defined with respect to the access of
on-chip memory and prevents unauthorized copying of proprietary code or data.
The device is secure when CPU access to the on-chip secure memory locations is restricted. When
secure, two levels of protection are possible, depending on where the program counter is currently
pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked
(i.e., through the emulator). This allows secure code to access secure data. Conversely, if code is running
from nonsecure memory, all accesses to secure memories are blocked. User code can dynamically jump
in and out of secure memory, thereby allowing secure function calls from nonsecure memory. Similarly,
interrupt service routines can be placed in secure memory, even if the main program loop is run from
nonsecure memory.
Security is protected by a password of 128-bits of data (eight 16-bit words) that is used to secure or
unsecure the device. This password is stored at the end of flash in 8 words referred to as the password
locations.
The device is unsecured by executing the password match flow (PMF), described Section 2.3.2 . Table 2-1
shows the levels of security.
Table 2-1. Security Levels
PMF Executed Operating Mode Program Fetch Security Description
With Correct Location
Password?
No Secure Outside secure memory Only instruction fetches by the CPU are allowed to secure
memory. In other words, code can still be executed, but not
read
No Secure Inside secure memory CPU has full access.
JTAG port cannot read the secured memory contents.
Yes Not Secure Anywhere Full access for CPU and JTAG port to secure memory
The password is stored in code security password locations (PWL) in flash memory (0x33 FFF8 -
0x33 FFFF). These locations store the password predetermined by the system designer.
If the password locations have all 128 bits as ones, the device is labeled unsecure. Since new flash
devices have erased flash (all ones), only a read of the password locations is required to bring the device
into unsecure mode. If the password locations have all 128 bits as zeros, the device is secure, regardless
of the contents of the KEY registers. Do not use all zeros as a password or reset the device during an
erase of the flash. Resetting the device during an erase routine can result in either an all zero or unknown
password. If a device is reset when the password locations are all zeros, the device cannot be unlocked
by the password match flow described in Section 2.3.2 . Using a password of all zeros will seriously limit
your ability to debug secure code or reprogram the flash.
Note: If a device is reset while the password locations are all zero or an unknown value, the device
will be permanently locked unless a method to run the flash erase routine from secure
SARAM is embedded into the flash or OTP. Care must be taken when implementing this
procedure to avoid introducing a security hole.
User accessible registers (eight 16-bit words) that are used to unsecure the device are referred to as key
registers. These registers are mapped in the memory space at addresses 0x00 0AE0 - 0x00 0AE7 and
are EALLOW protected.
28 Code Security Module (CSM) SPRUFB0C – September 2007 – Revised May 2009
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