1.2.1 Flash and OTP Performance
1.2.2 Flash Pipeline Mode
Flash and OTP Power Modes
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The duration of the delay is determined by the FSTDBYWAIT and FACTIVEWAIT registers. Moving from
the sleep state to a standby state is delayed by a count determined by the FSTDBYWAIT register. Moving
from the standby state to the active state is delayed by a count determined by the FACTIVEWAIT register.
Moving from the sleep mode (lowest power) to the active mode (highest power) is delayed by
FSTDBYWAIT + FACTIVEWAIT. These registers should be left in their default state.
CPU read or data fetch operations to the flash/OTP can take one of the following forms:
• 32-bit instruction fetch
• 16-bit or 32-bit data space read
• 16-bit program space read
Once flash is in the active power state, then a read or fetch access to the bank memory map area can be
classified as a flash access or an OTP access.
The main flash array is organized into rows and columns. The rows contain 2048 bits of information.
Accesses to flash and OTP are one of three types:
1. Flash Memory Random Access
The first access to a 2048 bit row is considered a random access.
2. Flash Memory Paged Access
While the first access to a row is considered a random access, subsequent accesses within the same
row are termed paged accesses.
The number of wait states for both a random and a paged access can be configured by programming
the FBANKWAIT register. The number of wait states used by a random access is controlled by the
RANDWAIT bits and the number of wait states used by a paged access is controlled by the
PAGEWAIT bits. The FBANKWAIT register defaults to a worst-case wait state count and, thus, needs
to be initialized for the appropriate number of wait states to improve performance based on the CPU
clock rate and the access time of the flash. The flash supports 0-wait accesses when the PAGEWAIT
bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access
time. To determine the random and paged access time requirements, refer to the Data Manual for your
particular device.
3. OTP Access
Read or fetch accesses to the OTP are controlled by the OTPWAIT bits in the FOTPWAIT register.
Accesses to the OTP take longer than the flash and there is no paged mode. To determine OTP
access time requirements, see the data manual for your particular device.
Some other points to keep in mind when working with flash:
• CPU writes to the flash or OTP memory map area are ignored. They complete in a single cycle.
• When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
• Reads of the CSM password locations are hardwired for 16 wait-states. The PAGEWAIT and
RANDOMWAIT bits have no effect on these locations. See Chapter 2 for more information on the
CSM.
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash pipeline mode has been
implemented. The flash pipeline feature is disabled by default. Setting the ENPIPE bit in the FOPT register
enables this mode. The flash pipeline mode is independent of the CPU pipeline.
18 Flash and OTP Memory Blocks SPRUFB0C – September 2007 – Revised May 2009
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