GPBDAT
(latch)
GPBCLEAR
GPBTOGGLE
GPBQSEL1/2
Qual
GPBMUX1/2
SYSCLKOUT
GPIO34
to
GPIO63
Pins
PU
XRS
0 = Input , 1 = Output
Sync
XINT Inputî˜ Signals
(XREADY,î˜ XD31:16_IN)
GPBDIR
(latch)
01
11
01
01
0x
1x
01
GPBCTRL
2
2
10
Perpheralî˜ 1î˜ input
N/C
(defaultî˜ onî˜ reset)
(defaultî˜ onî˜ reset)
GPIOx_OUT
GPIOx_DIR
GPBPUD
0 = enableî˜ PU
1 = disableî˜ PU
(disabledî˜ afterî˜ reset)
async
(asyncî˜ disable
whenî˜ low)
0x
1x
11
10
XINTFî˜ Outputî˜ Signals
(XR/ , , ,
, /XA0,
XA7.1,î˜ XD31:16_OUT)
Wî˜ î˜ XZCS0î˜ î˜ XZCS7
XWE0î˜ î˜ XWE1
N/C
N/C
Peripheralî˜ 1î˜ output
Peripheralî˜ 1î˜ outputî˜ enable
GPBSET
(defaultî˜ onî˜ reset)
3î˜ samples
6î˜ samples
00
00
00
00
XRS
Defaultî˜ atî˜ Reset
XINTFî˜ Outputî˜ Enables
(XD_OEî˜ orî˜ 1)
External
interrupt
MUX
GPIOî˜ XINT6SEL
GPIOî˜ XINT7SEL
GPIOî˜ XINT5SEL
GPIOî˜ XINT4SEL
GPIOî˜ XINT3SEL
PIE
GPBDAT (read)
High-
Impedance
Output
Control
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GPIO Module Overview
Figure 4-4. GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged)
A The shaded area is disabled in the above GPIOs when the GPIOINENCLK bit is cleared to "0" in the PCLKCR3
register and the respective pin is configured as an output. This is to reduce power consumption when a pin is
configured as an output. Clearing the GPIOINCLK bit will reset the sync and qualification logic so no residual value is
left.
B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode).
Any state will get flushed by the circuit eventually.
SPRUFB0C – September 2007 – Revised May 2009 General-Purpose Input/Output (GPIO) 69
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