32-Bit CPU Timers 0/1/2
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Figure 3-21. TIMERxTIM Register (x = 0, 1, 2)
15 0
TIM
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-19. TIMERxTIM Register Field Descriptions
Bits Field Description
15-0 TIM CPU-Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit count
of the timer. The TIMH register holds the high 16 bits of the current 32-bit count of the timer. The TIMH:TIM
decrements by one every (TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer prescale
divide-down value. When the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded with the
period value contained in the PRDH:PRD registers. The timer interrupt (TINT) signal is generated.
Figure 3-22. TIMERxTIMH Register (x = 0, 1, 2)
15 0
TIMH
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-20. TIMERxTIMH Register Field Descriptions
Bits Field Description
15-0 TIMH See description for TIMERxTIM.
Figure 3-23. TIMERxPRD Register (x = 0, 1, 2)
15 0
PRD
R/W-0xFFFF
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-21. TIMERxPRD Register Field Descriptions
Bits Field Description
15-0 PRD CPU-Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period. The
PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to zero, the
TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers, at the start of
the next timer input clock cycle (the output of the prescaler). The PRDH:PRD contents are also loaded into
the TIMH:TIM when you set the timer reload bit (TRB) in the Timer Control Register (TCR).
Figure 3-24. TIMERxPRDH Register (x = 0, 1, 2)
15 0
PRDH
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Clocking62 SPRUFB0C – September 2007 – Revised May 2009
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