PIE Interrupt Registers
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Table 6-12. Interrupt Enable Register (IER) — CPU Register Field Descriptions (continued)
Bits Field Value Description
3 INT4 Interrupt 4 enable.INT4 enables or disables CPU interrupt level INT4.
0 Level INT4 is disabled
1 Level INT4 is enabled
2 INT3 Interrupt 3 enable.INT3 enables or disables CPU interrupt level INT3.
0 Level INT3 is disabled
1 Level INT3 is enabled
1 INT2 Interrupt 2 enable.INT2 enables or disables CPU interrupt level INT2.
0 Level INT2 is disabled
1 Level INT2 is enabled
0 INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1.
0 Level INT1 is disabled
1 Level INT1 is enabled
The Debug Interrupt Enable Register (DBGIER) is used only when the CPU is halted in real-time
emulation mode. An interrupt enabled in the DBGIER is defined as a time-critical interrupt. When the CPU
is halted in real-time mode, the only interrupts that are serviced are time-critical interrupts that are also
enabled in the IER. If the CPU is running in real-time emulation mode, the standard interrupt-handling
process is used and the DBGIER is ignored.
As with the IER, you can read the DBGIER to identify enabled or disabled interrupts and write to the
DBGIER to enable or disable interrupts. To enable an interrupt, set its corresponding bit to 1. To disable
an interrupt, set its corresponding bit to 0. Use the PUSH DBGIER instruction to read from the DBGIER
and POP DBGIER to write to the DBGIER register. At reset, all the DBGIER bits are set to 0.
Figure 6-13. Debug Interrupt Enable Register (DBGIER) — CPU Register
15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 6-13. Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions
Bits Field Value Description
15 RTOSINT Real-time operating system interrupt enable. RTOSINT enables or disables the CPU RTOS
interrupt.
0 Level INT6 is disabled
1 Level INT6 is enabled
14 DLOGINT . Data logging interrupt enable. DLOGINT enables or disables the CPU data logging interrupt
0 Level INT6 is disabled
1 Level INT6 is enabled
13 INT14 . Interrupt 14 enable. INT14 enables or disables CPU interrupt level INT14
0 Level INT14 is disabled
1 Level INT14 is enabled
12 INT13 Interrupt 13 enable. INT13 enables or disables CPU interrupt level INT13.
0 Level INT13 is disabled
1 Level INT13 is enabled
146 Peripheral Interrupt Expansion (PIE) SPRUFB0C – September 2007 – Revised May 2009
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