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PIE Interrupt Registers
Table 6-13. Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions (continued)
Bits Field Value Description
11 INT12 Interrupt 12 enable. INT12 enables or disables CPU interrupt level INT12.
0 Level INT12 is disabled
1 Level INT12 is enabled
10 INT11 Interrupt 11 enable. INT11 enables or disables CPU interrupt level INT11.
0 Level INT11 is disabled
1 Level INT11 is enabled
9 INT10 Interrupt 10 enable. INT10 enables or disables CPU interrupt level INT10.
0 Level INT10 is disabled
1 Level INT10 is enabled
8 INT9 Interrupt 9 enable. INT9 enables or disables CPU interrupt level INT9.
0 Level INT9 is disabled
1 Level INT9 is enabled
7 INT8 Interrupt 8 enable. INT8 enables or disables CPU interrupt level INT8.
0 Level INT8 is disabled
1 Level INT8 is enabled
6 INT7 Interrupt 7 enable. INT7 enables or disables CPU interrupt level INT77.
0 Level INT7 is disabled
1 Level INT7 is enabled
5 INT6 Interrupt 6 enable. INT6 enables or disables CPU interrupt level INT6.
0 Level INT6 is disabled
1 Level INT6 is enabled
4 INT5 Interrupt 5 enable.INT5 enables or disables CPU interrupt level INT5.
0 Level INT5 is disabled
1 Level INT5 is enabled
3 INT4 Interrupt 4 enable.INT4 enables or disables CPU interrupt level INT4.
0 Level INT4 is disabled
1 Level INT4 is enabled
2 INT3 Interrupt 3 enable.INT3 enables or disables CPU interrupt level INT3.
0 Level INT3 is disabled
1 Level INT3 is enabled
1 INT2 Interrupt 2 enable.INT2 enables or disables CPU interrupt level INT2.
0 Level INT2 is disabled
1 Level INT2 is enabled
0 INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1.
0 Level INT1 is disabled
1 Level INT1 is enabled
SPRUFB0C – September 2007 – Revised May 2009 Peripheral Interrupt Expansion (PIE) 147
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