EALLOW-Protected Registers
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Table 5-10. EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers
Name Address Size Description
(x16)
PLLSTS 0x7011 1 PLL Status Register
HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler Register for HSPCLK Clock
LOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler Register for HSPCLK Clock
PCLKCR0 0x701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x701D 1 Peripheral Clock Control Register 1
LPMCR0 0x701E 1 Low Power Mode Control Register 0
PCLKCR3 0x7020 1 Peripheral Clock Control Register 3
PLLCR 0x7021 1 PLL Control Register
SCSR 0x7022 1 System Control and Status Register
WDCNTR 0x7023 1 Watchdog Counter Register
WDKEY 0x7025 1 Watchdog Reset Key Register
WDCR 0x7029 1 Watchdog Control Register
Table 5-11. EALLOW-Protected GPIO MUX Registers
Name Address Size Description
(x16)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to GPIO31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to GPIO15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to GPIO31)
GPAMUX1 0x6F86 2 GPIO A Mux 1 Register (GPIO0 to GPIO15)
GPAMUX2 0x6F88 2 GPIO A Mux 2 Register (GPIO16 to GPIO31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to GPIO31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to GPIO31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to GPIO35)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to GPIO35)
GPBQSEL2 0x6F94 2 Reserved
GPBMUX1 0x6F96 2 GPIO B Mux 1 Register (GPIO32 to GPIO35)
GPBMUX2 0x6F98 2 Reserved
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to GPIO35)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to GPIO35)
GPCMUX1 0x6FA6 2 GPIO C Mux 1 Register (GPIO64 to 79)
GPCMUX2 0x6FA8 2 GPIO C Mux 2 Register (GPIO80 to 87)
GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64 to 87)
GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64 to 87)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to GPIO31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to GPIO31)
GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to GPIO31)
GPIOXINT3SEL 0x6FE3 1 XINT3 GPIO Input Select Register (GPIO32 to GPIO63)
GPIOXINT4SEL 0x6FE4 1 XINT4 GPIO Input Select Register (GPIO32 to GPIO63)
GPIOXINT5SEL 0x6FE5 1 XINT5 GPIO Input Select Register (GPIO32 to GPIO63)
GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to GPIO63)
GPIOXINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to GPIO63)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to GPIO31)
Peripheral Frames114 SPRUFB0C – September 2007 – Revised May 2009
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