Texas Instruments TMS320x2833 series User Manual

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4-14 GPIO Port A Qualification Control (GPACTRL) Register ............................................................ 94
4-15 GPIO Port B Qualification Control (GPBCTRL) Register ............................................................ 95
4-16 GPIO Port A Qualification Select 1 (GPAQSEL1) Register........................................................... 96
4-17 GPIO Port A Qualification Select 2 (GPAQSEL2) Register........................................................... 96
4-18 GPIO Port B Qualification Select 1 (GPBQSEL1) Register........................................................... 97
4-19 GPIO Port B Qualification Select 2 (GPBQSEL2) Register........................................................... 97
4-20 GPIO Port A Direction (GPADIR) Register ............................................................................. 98
4-21 GPIO Port B Direction (GPBDIR) Register ............................................................................. 98
4-22 GPIO Port C Direction (GPCDIR) Register ............................................................................ 99
4-23 GPIO Port A Pullup Disable (GPAPUD) Registers .................................................................. 100
4-24 GPIO Port B Pullup Disable (GPBPUD) Registers .................................................................. 100
4-25 GPIO Port C Pullup Disable (GPCPUD) Registers .................................................................. 101
4-26 GPIO Port A Data (GPADAT) Register ............................................................................... 101
4-27 GPIO Port B Data (GPBDAT) Register ............................................................................... 102
4-28 GPIO Port C Data (GPCDAT) Register ............................................................................... 103
4-29 GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers ....................... 104
4-30 GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers ....................... 105
4-31 GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers ...................... 106
4-32 GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers ............................. 107
4-33 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register ................................................ 108
5-1 Device Configuration (DEVICECNF) Register ........................................................................ 116
5-2 Part ID Register ........................................................................................................... 117
5-3 CLASSID Register ........................................................................................................ 117
5-4 REVID Register ........................................................................................................... 117
6-1 Overview: Multiplexing of Interrupts Using the PIE Block ........................................................... 122
6-2 Typical PIE/CPU Interrupt Response - INTx.y ........................................................................ 124
6-3 Reset Flow Diagram ...................................................................................................... 126
6-4 PIE Interrupt Sources and External Interrupts XINT1/XINT2 ....................................................... 127
6-5 PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) ................................................... 128
6-6 Multiplexed Interrupt Request Flow Diagram ......................................................................... 131
6-7 PIECTRL Register (Address CE0) ..................................................................................... 140
6-8 PIE Interrupt Acknowledge Register (PIEACK) Register (Address CE1) ......................................... 140
6-9 PIEIFRx Register (x = 1 to 12) .......................................................................................... 141
6-10 PIEIERx Register (x = 1 to 12) .......................................................................................... 141
6-11 Interrupt Flag Register (IFR) — CPU Register ....................................................................... 143
6-12 Interrupt Enable Register (IER) — CPU Register .................................................................... 145
6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register ..................................................... 146
6-14 External Interrupt n Control Register (XINT nCR) .................................................................... 148
6-15 External NMI Interrupt Control Register (XNMICR) — Address 7077h ............................................ 148
6-16 External Interrupt 1 Counter (XINT1CTR) (Address 7078h) ........................................................ 149
6-17 External Interrupt 2 Counter (XINT2CTR) (Address 7079h) ........................................................ 149
6-18 External NMI Interrupt Counter (XNMICTR) (Address 707Fh) ..................................................... 150
List of Figures6 SPRUFB0C – September 2007 – Revised May 2009
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Texas Instruments TMS320x2833 series Specifications

General

Brand	Texas Instruments
Model	TMS320x2833 series
Category	Controller
Language	English