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List of Tables
1-1 Flash/OTP Configuration Registers ...................................................................................... 21
1-2 Flash Options Register (FOPT) Field Descriptions .................................................................... 22
1-3 Flash Power Register (FPWR) Field Descriptions ..................................................................... 22
1-4 Flash Status Register (FSTATUS) Field Descriptions ................................................................. 23
1-5 Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 24
1-6 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions ............................. 24
1-7 Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 25
1-8 OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 26
2-1 Security Levels ............................................................................................................. 28
2-2 Resources Affected by the CSM ......................................................................................... 30
2-3 Resources Not Affected by the CSM .................................................................................... 30
2-4 Code Security Module (CSM) Registers ................................................................................ 31
2-5 CSM Status and Control Register (CSMSCR) Field Descriptions ................................................... 32
3-1 PLL, Clocking, Watchdog, and Low-Power Mode Registers ........................................................ 39
3-2 Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions ................................................ 39
3-3 Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 41
3-4 Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions ................................................ 43
3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions .............................................. 44
3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions ................................... 44
3-7 Possible PLL Configuration Modes ...................................................................................... 46
3-8 PLLCR Bit Descriptions ................................................................................................... 51
3-9 PLL Status Register (PLLSTS) Field Descriptions ..................................................................... 51
3-10 Low-Power Mode Summary .............................................................................................. 53
3-11 Low Power Modes ......................................................................................................... 53
3-12 Low Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 54
3-13 Example Watchdog Key Sequences ..................................................................................... 56
3-14 System Control and Status Register (SCSR) Field Descriptions .................................................... 58
3-15 Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 59
3-16 Watchdog Reset Key Register (WDKEY) Field Descriptions ......................................................... 59
3-17 Watchdog Control Register (WDCR) Field Descriptions .............................................................. 59
3-18 CPU-Timers 0, 1, 2 Configuration and Control Registers ............................................................. 61
3-19 TIMERxTIM Register Field Descriptions ................................................................................ 62
3-20 TIMERxTIMH Register Field Descriptions .............................................................................. 62
3-21 TIMERxPRD Register Field Descriptions ............................................................................... 62
3-22 TIMERxPRDH Register Field Descriptions ............................................................................. 63
3-23 TIMERxTCR Register Field Descriptions ............................................................................... 63
3-24 TIMERxTPR Register Field Descriptions ............................................................................... 64
3-25 TIMERxTPRH Register Field Descriptions.............................................................................. 64
4-1 GPIO Control Registers ................................................................................................... 71
4-2 GPIO Interrupt and Low Power Mode Select Registers ............................................................... 71
4-3 GPIO Data Registers ...................................................................................................... 73
4-4 Sampling Period ............................................................................................................ 75
4-5 Sampling Frequency ....................................................................................................... 75
4-6 Case 1: Three-Sample Sampling Window Width ...................................................................... 76
4-7 Case 2: Six-Sample Sampling Window Width .......................................................................... 76
4-8 Default State of Peripheral Input ......................................................................................... 79
4-9 GPIOA MUX ................................................................................................................ 80
4-10 GPIOB MUX ................................................................................................................ 81
4-11 GPIOC MUX ................................................................................................................ 82
SPRUFB0C – September 2007 – Revised May 2009 List of Tables 7
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