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4-12 GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions .............................................. 83
4-13 GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ....................................................... 85
4-14 GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ....................................................... 87
4-15 GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions ....................................................... 89
4-16 GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions ...................................................... 91
4-17 GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions ...................................................... 92
4-18 GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions ....................................... 94
4-19 GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions ....................................... 95
4-20 GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions .................................... 96
4-21 GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions .................................... 96
4-22 GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions .................................... 97
4-23 GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions .................................... 97
4-24 GPIO Port A Direction (GPADIR) Register Field Descriptions ....................................................... 98
4-25 GPIO Port B Direction (GPBDIR) Register Field Descriptions ....................................................... 99
4-26 GPIO Port C Direction (GPCDIR) Register Field Descriptions ....................................................... 99
4-27 GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 100
4-28 GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 100
4-29 GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions .................................... 101
4-30 GPIO Port A Data (GPADAT) Register Field Descriptions .......................................................... 102
4-31 GPIO Port B Data (GPBDAT) Register Field Descriptions .......................................................... 102
4-32 GPIO Port C Data (GPCDAT) Register Field Descriptions ......................................................... 103
4-33 GPIO Port A Set (GPASET) Register Field Descriptions ............................................................ 104
4-34 GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 104
4-35 GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 104
4-36 GPIO Port B Set (GPBSET) Register Field Descriptions ............................................................ 105
4-37 GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 105
4-38 GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 105
4-39 GPIO Port C Set (GPCSET) Register Field Descriptions ........................................................... 106
4-40 GPIO Port C Clear (GPCCLEAR) Register Field Descriptions ..................................................... 106
4-41 GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions ................................................. 106
4-42 GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions ..................................... 107
4-43 XINT1/XINT2 Interrupt Select and Configuration Registers ......................................................... 107
4-44 GPIO XINT3 - XINT7 Interrupt Select (GPIOXINTnSEL) Register Field Descriptions .......................... 107
4-45 XINT3 - XINT7 Interrupt Select and Configuration Registers ....................................................... 107
4-46 GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions ...................................... 108
4-47 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions .......................... 108
5-1 Peripheral Frame 0 Registers .......................................................................................... 110
5-2 Peripheral Frame 1 Registers ........................................................................................... 110
5-3 Peripheral Frame 2 Registers ........................................................................................... 111
5-4 Peripheral Frame 3 Registers ........................................................................................... 111
5-5 Access to EALLOW-Protected Registers .............................................................................. 112
5-6 EALLOW-Protected Device Emulation Registers..................................................................... 112
5-7 EALLOW-Protected Flash/OTP Configuration Registers ............................................................ 112
5-8 EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 113
5-9 EALLOW-Protected PIE Vector Table ................................................................................. 113
5-10 EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 114
5-11 EALLOW-Protected GPIO MUX Registers ........................................................................... 114
5-12 EALLOW-Protected eCAN Registers .................................................................................. 115
5-13 EALLOW-Protected ePWM1 - ePWM 6 Registers .................................................................... 115
5-14 XINTF Registers ......................................................................................................... 115
5-15 Device Emulation Registers ............................................................................................. 116
8 List of Tables SPRUFB0C – September 2007 – Revised May 2009
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