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5-16 DEVICECNF Register Field Descriptions.............................................................................. 116
5-17 PARTID Register Field Descriptions ................................................................................... 117
5-18 CLASSID Register Description .......................................................................................... 117
5-19 REVID Register Field Descriptions ..................................................................................... 118
5-20 PROTSTART and PROTRANGE Registers........................................................................... 118
5-21 PROTSTART Valid Values ............................................................................................. 118
5-22 PROTRANGE Valid Values ............................................................................................. 119
6-1 Enabling Interrupt ......................................................................................................... 124
6-2 Interrupt Vector Table Mapping ........................................................................................ 125
6-3 Vector Table Mapping After Reset Operation ........................................................................ 125
6-4 PIE MUXed Peripheral Interrupt Vector Table ........................................................................ 133
6-5 PIE Vector Table .......................................................................................................... 134
6-6 PIE Configuration and Control Registers .............................................................................. 139
6-7 PIECTRL Register Address Field Descriptions ....................................................................... 140
6-8 PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions ................................................. 140
6-9 PIEIFRx Register Field Descriptions ................................................................................... 141
6-10 PIEIERx Register (x = 1 to 12) Field Descriptions ................................................................... 142
6-11 Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 143
6-12 Interrupt Enable Register (IER) — CPU Register Field Descriptions .............................................. 145
6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 146
6-14 External Interrupt n Control Register (XINT nCR) Field Descriptions .............................................. 148
6-15 External NMI Interrupt Control Register (XNMICR) Field Descriptions ............................................ 148
6-16 XNMICR Register Settings and Interrupt Sources ................................................................... 149
6-17 External Interrupt 1 Counter (XINT1CTR) Field Descriptions ....................................................... 149
6-18 External Interrupt 2 Counter (XINT2CTR) Field Descriptions ....................................................... 150
6-19 External NMI Interrupt Counter (XNMICTR) Field Descriptions .................................................... 150
A-1 Changes Made in This Revision ........................................................................................ 151
SPRUFB0C – September 2007 – Revised May 2009 List of Tables 9
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