Register Bit Definitions
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Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions (continued)
Bit Field Value Description
23:22 GPIO59 Configure this pin as:
00 GPIO 59 - general purpose I/O 59 (default)
01 MFSRA - McBSP-A receive frame synch (I/O)
10 or XD20 - External interface data line 20 (I/O)
11
21:20 GPIO58 Configure this pin as:
00 GPIO 58 - general purpose I/O 58 (default)
01 MCLKRA - McBSP-A receive clock (I/O)
10 or XD21 - External interface data line 21 (I/O)
11
19:18 GPIO57 Configure this pin as:
00 GPIO 57 - general purpose I/O 57 (default)
01 SPISTEA - SPI-A slave transmit enable (I/O)
10 or XD22 - External interface data line 22 (I/O)
11
17:16 GPIO56 Configure this pin as:
00 GPIO 56 - general purpose I/O 56 (default)
01 SPICLKA - SPI-A clock input/output (I/O)
10 or XD23 - External interface data line 23 (I/O)
11
15:14 GPIO55 Configure this pin as:
00 GPIO 55 - general purpose I/O 55 (default)
01 SPISOMIA - SPI-A slave out, master in (I/O)
10 or XD24 - External interface data line 24 (I/O)
11
13:12 GPIO54 Configure this pin as:
00 GPIO 54 - general purpose I/O 54 (default)
01 SPISIMOA - SPI slave in, master out (I/O)
10 or XD25 - External interface data line 25 (I/O)
11
11:10 GPIO53 Configure this pin as:
00 GPIO 53 - general purpose I/O 53 (default)
01 EQEP1I - Enhanced QEP1 index (I/O)
10 or XD26 - External interface data line 26 (I/O)
11
9:8 GPIO52 Configure this pin as:
00 GPIO 52 - general purpose I/O 52 (default)
01 EQEP1S - Enhanced QEP1 strobe (I/O)
10 or XD27External interface data line 27 (I/O)
11
7:6 GPIO51 Configure this pin as:
00 GPIO 51 - general purpose I/O 51 (default)
01 EQEP1B - Enhanced QEP1 input B (I)
10 or XD28 - External interface data line 28 (I/O)
11
5:4 GPIO50 Configure this pin as:
00 GPIO 50 - general purpose I/O 50 (default)
01 EQEP1A - Enhanced QEP1 input A (I)
10 or XD29 - External interface data line 29 (I/O)
11
90 General-Purpose Input/Output (GPIO) SPRUFB0C – September 2007 – Revised May 2009
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