ZiLOG Z8

Z8 Microcontrollers
List of Figures ZiLOG
Figure Title Page
xii UM001601-0803
Prescaler 0 Reset ......................................................................................................................6-12
Timer Mode Register Reset .......................................................................................................6-12
Chapter 7. Interrupts
Interrupt Control Registers ..........................................................................................................7-1
Interrupt Block Diagram ...............................................................................................................7-1
Interrupt Sources IRQ0-IRQ2 Block Diagram ..............................................................................7-2
Interrupt Source IRQ3 Block Diagram .........................................................................................7-3
IRQ Register Logic ......................................................................................................................7-4
Interrupt Request Timing .............................................................................................................7-4
Interrupt Priority Register ............................................................................................... 7-5
Interrupt Mask Register ...............................................................................................................7-6
Interrupt Request Register ..........................................................................................................7-7
IRQ Reset Functional Logic Diagram ..........................................................................................7-8
Effects of an Interrupt on the STACK ..........................................................................................7-9
Interrupt Vectoring .....................................................................................................................7-10
Z8 Interrupt Acknowledge Timing .............................................................................................7-11
Chapter 8. Power-Down Modes
STOP-Mode Recovery Register
(Write-Only Except Bit D7, Which Is Read-Only) ..............................................................8-3
STOP-Mode Recovery Source ....................................................................................................8-4
Chapter 9. Serial I/O
UART Block Diagram ..................................................................................................................9-1
Port 3 Mode Register (P3M) and Bit-Rate Generation ................................................................9-2
Bit Rate Divide Chain ..................................................................................................... 9-2
Prescaler 0 Register (PRE0) Bit-Rate Generation ......................................................................9-3
Timer Mode Register (TMR) Bit Rate Generation .......................................................................9-4
Receiver Timing ...........................................................................................................................9-4
Receiver Data Formats .................................................................................................... 9-5
Port 3 Mode Register (P3M) Parity ..............................................................................................9-5
Transmitter Data Formats ............................................................................................................9-6
SIO Register Reset ......................................................................................................................9-7
P3M Register Reset ....................................................................................................................9-7
SPI Control Register (SCON) ......................................................................................................9-8
SPI System Configuration .........................................................................................................9-10
SPI Timing .................................................................................................................................9-11
SPI Logic ...................................................................................................................................9-12
SPI Data In/Out Configuration ...................................................................................................9-13
SPI Clock / SPI Slave Select Output Configuration ...................................................................9-14