Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-13
ADD
ADD
ADD
Add
ADD dst, src
Instruction Format:
Operation:
dst <— dst + src
The source operand is added to the destination operand. Two’s complement addition is performed. The sum is
stored in the destination operand. The contents of the source operand are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the
OpCode.
Example:
If Working Register R3 contains 16H and Working Register R11 contains 20H, the statement:
ADD R3, R11
OpCode: 02 3B
leaves the value 36H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is zero; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the
opposite sign; cleared otherwise.
D: Always cleared.
H: Set if there is a carry from the most significant bit of the low order four bits of the result; cleared
otherwise.
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