Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-21
COM
COMPLEMENT
COM
Complement
COM dst
Instruction Format:
Operation:
dst <— NOT dst
The contents of the destination operand are complemented (one’s complement). All 1 bits are changed to 0, and all
0 bits are changed to 1.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Register 08H contains 24H (00100100B), the statement:
COM 08H
Op Code: 60 08
leaves the value DBH (11011011) in Register 08H. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Register 08H contains 24H, and Register 24H contains FFH (11111111B), the statement:
COM @08H
Op Code: 61 08
leaves the value 00H (00000000B) in Register 24H. The Z Flag is set, and the V and S Flags are cleared.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Always reset to 0.
D: Unaffected
H: Unaffected
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