Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-37
LD
LOAD
LD
Load
LD dst, src
Instruction Format:
Operation:
dst <— src
The contents of the source operand are loaded into the destination operand. The contents of the source operand are
not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags: C: Unaffected
Z: Unaffected
S: Unaffected
V: Unaffected
D: Unaffected
H: Unaffected
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