Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-47
OR
LOGICAL OR
OR
Logical OR
OR dst, src
Instruction Format:
Operation:
dst <— dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the destination
operand. The contents of the source operand are not affected. The OR operation results in a one bit being stored
whenever either of the corresponding bits in the two operands is a one. Otherwise, a zero bit is stored.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH (10001101), the
statement:
OR R1, R14
Op Code: 42 1E
leaves the value BDH (10111101B) in Working Register R1. The S Flag is set, and the Z and V Flags are cleared.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the result of bit 7 is set; cleared otherwise
V: Always reset to 0
D: Unaffected
H: Unaffected
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