Z8 Microcontrollers
Instruction Descriptions and Formats ZiLOG
12-64 UM001601-0803
SRA
SHIFT RIGHT ARITHMETIC
SRA
Shift Right Arithmetic
SRA dst
Instruction Format:
Operation:
C <— dst(0)
dst(0) <— dst(1)
dst(1) <— dst(2)
dst(2) <— dst(3)
dst(3) <— dst(4)
dst(4) <— dst(5)
dst(5) <— dst(6)
dst(6) <— dst(7)
dst(7) <— dst(7)
An arithmetic shift right by one bit position is performed on the destination operand. Bit 0 replaces the C Flag. Bit
7 (the Sign bit) is unchanged and its value is shifted into bit 6.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags: C: Set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1).
Z: Set if the result is zero; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to 0.
D: Unaffected
H: Unaffected
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