ZiLOG Z8 - Page 66

Z8 Microcontrollers
I/O Ports ZiLOG
5-20 UM001601-0803
5.6 PORT HANDSHAKE (Continued)
Figure 5-24. Z8 Output Handshake
Valid Data
(Input To Z8)
State 1.
213
45
RDY
(Output From Z8)
DAV
(Output From Z8)
Data on Port
RDY input is High indicating that the I/O device is ready to accept data.
State 2.
The Z8 Writes to the port register to initiate a data transfer. Writing to the port outputs new data and
forces
DAV Low if and only if RDY is High.
State 3.
The I/O device forces RDY Low after latching the data. RDY Low causes an interrupt request to be generated.
The Z8 can write new data responses to RDY going Low; however, the data is not output until State 5.
State 4.
The
DAV output from the Z8 is driven High in response to RDY going Low.
State 5.
The DAV goes High, the I/O device is free to raise RDY High thus returning the interface to its initial state.