GDP-32
II
INSTRUCTION MANUAL
May 2002 Section 16, Page 4
16.2 RECEIVER LAYOUT
Figures 16.1 (a) and (b) are detailed block diagrams of the general layout of the receiver. The
package design separates the digital control circuit boards mounted to the front panel from the
analog acquisition cards and the timing and calibration card that are inserted into the card cage.
The analog system of the GDP-32
II
is comprised of the Analog I/O Panel through which signals
are connected to as many as 16 analog boards. The analog boards provide necessary gain and
filtering prior to A/D conversion. They are mounted in the card cage together with the timing
and calibration card.
Each analog card contains:
Individual power supply
High-speed sample and hold circuit
Analog to Digital converter (ADC)
The timing and calibration card contains:
Counter chains that generate the binary detection frequencies selectable through the
program menus.
Digital to Analog converter (DAC) for generating precision analog test signals for
calibration purposes.
GPS synchronizing Circuitry (BD 288)
The ribbon cables, located between the front panel and the lid, route the amplified and filtered
analog signals from each of the analog boards to the panel meter switch.
An oven-stabilized 4.980736 MHz crystal oscillator is mounted directly to the timing board
(BD244 or BD288) in the large case GDP-32
II
. In the small case GDP-32
II
, the crystal is
mounted next to the battery compartment.
Basic control and monitoring of the receiver function is handled by the keyboard and the Front
Panel LCD display. Mounted to the underside of the panel is a 66 MHz 586 Card-PC single
board computer together with a motherboard (BD287). The front panel assembly consists of the
Front Panel, the MPU board and BD287 and constitutes the complete system for digital control
of analog data acquisition.
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