ABB Relion 670 series - Page 46

AND
PHSEL
PUND_AB-cont.
PUND_BC-cont.
PUND_CA-cont.
PUND_AG-cont.
PUND_BG-cont.
PUND_CG-cont.
STZMPP-cont.
PUND_GND-cont.
1--BLOCK
LOVBZ
PU_ND
BLK-cont.
xx04000376_ansi.vsd
AB
BC
CA
AG
BG
CG
AND
AND
AND
AND
AND
OR
OR
AND
OR
OR
ANSI04000376 V1 EN
Figure 2: Logic diagram example with an outgoing -cont signal
or
or
or
AND
AND
AND
AND
BLK-cont.
PICKUP
PU_C
PU_B
PU_A
15 ms
0
15 ms
0
15 ms
0
15 ms
0
or
STND_AG-cont.
STND_BG-cont.
STND_CG-cont.
STND_AB-cont.
STND_BC-cont.
STND_CA-cont.
Xx04000377_ansi.vsd
ANSI04000377 V1 EN
Figure 3: Logic diagram example with an incoming -cont signal
Section 1 1MRK505222-UUS C
Introduction
40
Technical reference manual