ABB Relion 670 series - Page 529

a>b
a
b
Vpickup>
V
t
tReset1
t
t1
AND
TRST1
PU_ST1
OFF
Delay
ON
Delay
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN
Figure 267: Detailed logic diagram for step 1, Definite time delay, DT operation
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN
Figure 268: Example for Definite Time Delay stage 1 reset
1MRK505222-UUS C Section 8
Voltage protection
523
Technical reference manual