ABB Relion 670 series - Page 624

ANSI07000114-3-en.vsd
OperationSC = Enabled
TSTSC
BLKSC
BLOCK
T S T A U
T S Y
AUTOSYOK
P H
D I
F F
M E
FRDIFF
ME
VDIFFME
PHDIFFA
FRDIFFA
VOKSC
VDIFFSC
OR
AND
AND
AND
AND
AND
AND
VHighLineSC
VHighBusSC
VDiffSC
phaseAngleDifferenceValue
frequencyDifferenceValue
voltageDifferenceValue
1
1
1
AND
tSCA
PhaseDiffA
FreqDiffA
50 ms
0
0-60 ms
0
Note! Similar logic for Manual Synchronism check.
INADVCLS
PhDiff > 60°
PhDiff < 5°
AND
AND
100 ms
32 ms
0
ANSI07000114 V3 EN
Figure 309: Simplified logic diagram for the Auto Synchronism function
Synchronizing
When the function is set to OperationSynch = Enabled the measuring will be performed.
The function will compare the values for the bus and line voltage with the set values
for VHighBusSynch and VHighLineSynch, which is a supervision that the voltages are
both live. Also the voltage difference is checked to be smaller than the set value for
VDiffSynch, which is a p.u value of set voltage base values. If both sides are higher
than the set values and the voltage difference between bus and line is acceptable, the
measured values are compared with the set values for acceptable frequency
Section 12 1MRK505222-UUS C
Control
618
Technical reference manual