Allwinner A20 - Page 121

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 121 / 812
Offset: 0x60
Register Name: TMR5_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
Select the pre-scale of timer 5 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
3:2
R/W
0x1
TMR5_CLK_SRC.
Timer 5 Clock Source.
00: Low speed OSC,
01: OSC24M.
10: External CLKIN1
11: /.
1
R/W
0x0
TMR5_RELOAD.
Timer 5 Reload.
0: No effect, 1: Reload timer 5 Interval value.
0
R/W
0x0
TMR5_EN.
Timer 5 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to
internal register, and the current counter will count from
interval value to 0.
If the current counter does not reach the zero, the timer
enable bit is set to “0”, the current value counter will pause.
At least wait for 2 Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be
modified. If the timer is started again, and the Software hope
the current value register to down-count from the new interval
value, the reload bit and the enable bit should be set to 1 at
the same time.
Note:
1) If the clock source is External CLKIN, the interval value register is not used, the current value
register is an up counter that counts from 0;
2) The time between the timer disabled and enabled should be larger than 2*Tcycles(Tcycles= Timer
clock source/pre-scale).