Allwinner A20 - Page 122

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 122 / 812
1.9.3.18. TIMER 5 INTERVAL VALUE REGISTER
Offset: 0x64
Register Name: TMR5_INTV_VALUE_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
x
TMR5_INTV_VALUE.
Timer 5 Interval Value.
Note: When you set the value, please take into consideration the system clock and the timer clock
source.
1.9.3.19. TIMER 5 CURRENT VALUE REGISTER
Offset: 0x68
Register Name: TMR5_CUR_VALUE_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
x
TMR5_CUR_VALUE.
Timer 5 Current Value.
Note:
1) Timer 1 current value is a 32-bit down-counter(from interval value to 0). This register can be read
correctly if the PCLK is faster than 2*TimerFreq(TimerFreq = TimerClkSource/pre-scale);
2) Before timer 5 is enabled, timer 5 current value register needs to be written with zero.
1.9.3.20. AVS COUNTER CONTROL REGISTER(DEFAULT: 0X00000000)
Offset: 0x80
Register Name: AVS_CNT_CTL_REG
Bit
Read
/Write
Default
Description
31:1
0
/
/
/
9
R
0x0
AVS_CNT1_PS
Audio/Video Sync Counter 1 Pause Control
0: Not pause
1: Pause Counter 1
8
R/W
0x0
AVS_CNT0_PS
Audio/Video Sync Counter 0 Pause Control
0: Not pause
1: Pause Counter 0