Allwinner A20 - Page 123

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 123 / 812
Offset: 0x80
Register Name: AVS_CNT_CTL_REG
Bit
Read
/Write
Default
Description
7:2
/
/
/
1
R/W
0x0
AVS_CNT1_EN
Audio/Video Sync Counter 1 Enable/ Disable. The counter source
is OSC24M.
0: Disable
1: Enable
0
R/W
0x0
AVS_CNT0_EN
Audio/Video Sync Counter 1 Enable/ Disable. The counter source
is OSC24M.
0: Disable
1: Enable
1.9.3.21. AVS COUNTER 0 REGISTER(DEFAULT: 0X00000000)
Offset: 0x84
Register Name: AVS_CNT0_REG
Bit
Read
/Write
Default
Description
31:0
R/W
0x0
AVS_CNT0
Counter 0 for Audio/ Video Sync Application
The high 32 bits of the internal 33-bits counter register. The initial
value of the internal 33-bits counter register can be set by
software. The LSB bit of the 33-bits counter register should be
zero when the initial value is updated. It will count from the initial
value. The initial value can be updated at any time. It can also be
paused by setting AVS_CNT0_PS to ‘1’. When it is paused, the
counter won’t increase.
1.9.3.22. AVS COUNTER 1 REGISTER(DEFAULT: 0X00000000)
Offset: 0x88
Register Name: AVS_CNT1_REG
Bit
Read/Writ
e
Default
Description
31:0
R/W
0x0
AVS_CNT1
Counter 1 for Audio/ Video Sync Application
The high 32 bits of the internal 33-bits counter register. The
initial value of the internal 33-bits counter register can be set