Allwinner A20 - Page 124

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 124 / 812
Offset: 0x88
Register Name: AVS_CNT1_REG
Bit
Read/Writ
e
Default
Description
by software. The LSB bit of the 33-bits counter register should
be zero when the initial value is updated. It will count from the
initial value. The initial value can be updated at any time. It can
also be paused by setting AVS_CNT1_PS to ‘1’. When it is
paused, the counter won’t increase.
1.9.3.23. AVS COUNTER DIVISOR REGISTER(DEFAULT: 0X05DB05DB)
Offset: 0x8C
Register Name: AVS_CNT_DIV_REG
Bit
Read
/Write
Default
Description
31:28
/
/
/
27:16
R/W
0x5DB
AVS_CNT1_D
Divisor N for AVS Counter1
AVS CN1 CLK=24MHz/Divisor_N1.
Divisor N1 = Bit[27:16] + 1.
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another
12-bits counter. The 12-bits counter is used for counting the
cycle number of one 24Mhz clock. When the 12-bits counter
reaches (>= N) the divisor value, the internal 33-bits counter
register will increase 1 and the 12-bits counter will reset to
zero and restart again.
Notes: It can be configured by software at any time.
15:12
/
/
/
11:0
R/W
0x5DB
AVS_CNT0_D
Divisor N for AVS Counter0
AVS CN0 CLK=24MHz/Divisor_N0.
Divisor N0 = Bit[11:0] + 1
The number N is from 1 to 0x7ff. The zero value is reserved.
The internal 33-bits counter engine will maintain another
12-bits counter. The 12-bits counter is used for counting the
cycle number of one 24Mhz clock. When the 12-bits counter
reaches (>= N) the divisor value, the internal 33-bits counter
register will increase 1 and the 12-bits counter will reset to
zero and restart again.
Notes: It can be configured by software at any time.