Allwinner A20 - Page 126

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 126 / 812
Offset: 0x94
Register Name: WDOG_MODE_REG
Bit
Read/
Write
Default/Hex
Description
2
/
/
/
1
R/W
0x0
WDOG_RST_EN.
Watchdog Reset Enable.
0: No effect on the resets,
1: Enables the Watchdog to activate the system reset.
0
R/W
0x0
WDOG_EN.
Watchdog Enable.
0: No effect, 1: Enable the Watchdog.
1.9.3.26. LOSC CONTROL REGISTER (DEFAULT: 0X00004000)
Offset: 0x100
Register Name: LOSC_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
31:16
W
0x0
KEY_FIELD.
Key Field. This field should be filled with 0x16AA, then the bit 0
can be written with the new value.
15
R/W
0x0
CLK32K_AUTO_SWT_PEND.
CLK32K auto switch pending.
0: no effect, 1: auto switch pending.
14
R/W
0x1
CLK32K_AUTO_SWT_EN.
CLK32K auto switch enable.
0: Disable, 1: Enable.
13:10
/
/
/.
9
R/W
0x0
ALM_DDHHMMSS_ACCE.
ALARM DD-HH-MM-SS access.
After writing the ALARM DD-HH-MM-SS register, this bit is set
and it will be cleared until the real writing operation is finished.
8
R/W
0x0
RTC_HHMMSS_ACCE.
RTC HH-MM-SS access.
After writing the RTC HH-MM-SS register, this bit is set and it
will be cleared until the real writing operation is finished.
After writing the RTC YY-MM-DD register, the YY-MM-DD
register will be refreshed for at most one second.